1. Field of Invention
The inventive principles of this patent disclosure relate to a semiconductor memory device, and more particularly, to a circuit and method to provide stable refresh control at the trip point of a temperature sensor.
2. Description of the Related Art
Semiconductor devices have operational characteristics that vary with changes in temperature. Typical operational characteristics of semiconductor devices include current consumption and operating speed. As the temperature increases, the operating speed decreases. As the temperature decreases, current consumption increases.
These temperature characteristics are of great importance to volatile memory devices such as dynamic random access memories (DRAMs). Since DRAM cells experience increasing leakage current as temperature rises, data maintenance characteristics deteriorate due to charge loss, which reduces data maintenance time. Therefore, DRAMs require faster refresh operations at temperature increases.
Developments in electronic technologies have enabled portable electronic devices such as beepers, cellular phones, MP3 players, calculators, laptop computers, personal digital assistants (PDAs), etc., to be designed and manufactured cost-effectively. These portable electronic devices require direct current (DC) power which is supplied by at least one battery as an energy source.
It is most important that battery operated systems minimize power consumption. To this end, many devices have a sleep mode for saving power in which circuit components embedded in the battery operated systems are turned off. However, DRAMs embedded in battery operated systems must periodically refresh data stored in DRAM cells in order to continuously maintain the DRAM cell data.
The refresh period for a DRAM must be changed depending on temperature to reduce power consumption. For example, at lower temperatures where the current consumption increases, the refresh period is increased to reduce the relative number refresh operations so as to reduce the power consumption of the DRAM.
FIG. 1 is a block diagram of a conventional refresh control circuit 100. Referring to FIG. 1, the refresh control circuit 100 comprises a counter 110, a pulse generator 120, a temperature sensor 130, a refresh master block 140, and a wordline enable unit 150.
The counter 110 receives an oscillator clock signal (OSC) and generates a plurality of clock signals Q0, Q1, Q2, . . . Qn. The counter 110 will now be in detail described with reference to FIG. 2.
FIG. 2 is a block diagram of the counter 110 illustrated in FIG. 1. Referring to FIG. 2, the counter 110 comprises a plurality of serially connected divider circuits 201, 202, 203, 204, and 205. The first divider circuit CNT0 divides the OSC and generates the first clock signal Q0. The second divider circuit CNT1 divides the first clock signal Q0 and generates the second clock signal Q1. The third divider circuit CNT2 divides the second clock signal Q1 and generates the third clock signal Q2. The n+1st divider circuit CNTn divides the nth clock signal Qn-1 and generates the n+1st clock signal Qn. The n+1st clock signal Qn has the longest clock period.
FIG. 3 is a circuit diagram of the pulse generator 120 illustrated in FIG. 1. Referring to FIG. 3, the pulse generator 120 comprises a delay unit 310 that receives the n+1st clock signal Qn of the counter 110 and delays the n+1st clock signal Qn, a NAND gate 320 that receives an output of the delay unit 310 and the n+1st clock signal Qn, and first and second inverters 330 and 340 that receive an output of the NAND gate 320 and generates a temperature sensor enable signal PTENB. The first and second inverters 330 and 340 form a buffer. The temperature sensor enable signal PTENB is a pulse signal having a logic low section corresponding to a delayed time of the delay unit 310.
The temperature sensor 130 senses a present temperature of a DRAM chip in response to the temperature sensor enable signal PTENB. The temperature sensor 130 can have a plurality of trip points. For example, the temperature sensor 130 has two trip points and generates first and second temperature signals T45 and T85 according to the sensed temperature. The first temperature signal T45 is logic high when the sensed temperature is above 45° C., and is logic low when the sensed temperature is below 45° C. The second temperature signal T85 is logic high when the sensed temperature is above 85° C., and is logic low when the sensed temperature is below 85° C.
The refresh master block 140 selects one of the clock signals Q0, Q1, Q2, . . . Qn generated by the counter 110 in response to PTENB and the first and second temperature signals T45 and T85. The refresh master block 140 generates a refresh control signal SRFHP according to the selected clock signal, and generates a refresh signal PREF in response to the refresh control signal SRFHP. The wordline enable unit 150 enables wordlines (not shown) of memory cells in response to the refresh signal PREF.
The refresh control circuit 100 changes the frequency of refresh operations in response to the temperature of the surrounding DRAM chip based on the trip point of the temperature sensor 130. FIG. 4 illustrates a section of the temperature range in which erroneous refresh operations tend to occur. Referring to FIG. 4, an erroneous refresh operation section is around 45° C. An erroneous refresh operation will now be described in detail with reference to FIG. 5. FIG. 5 is a timing diagram of the operation of the reference period control circuit 100.
Referring to FIG. 5, a Qi clock signal, a Qj clock signal, and a Qn clock signal are shown among the clock signals Q0, Q1, Q2, . . . Qn. The Qi clock signal is selected according to an initially sensed chip temperature. The refresh control signal SRFHP is generated according to the Qi clock signal ({circle around (1)}). The refresh signal PREF having a logic high pulse is generated in response to a falling edge of the refresh control signal SRFHP ({circle around (2)}).
The temperature sensor enable signal PTENB is logic low in response to a rising edge of the Qn clock signal having the longest clock period ({circle around (3)}). The temperature sensor 130 is operated to sense a present temperature of the DRAM chip during a time when the temperature sensor enable signal PTENB is logic low.
When the temperature sensor enable signal PTENB changes from logic low to logic high ({circle around (4)}), the temperature sensor 130 selects the Qj clock signal according to the changed temperature. At this time, when a logic level of the presently selected Qj clock signal is different from that of the previously selected Qi clock signal, the refresh control signal SRFHP has a logic low level according to the Qi clock signal ({circle around (5)}), and has a logic high level according to the Qj clock signal ({circle around (6)}), thereby causing a short logic low pulse. The refresh signal PREF having a short logic high pulse is generated in response to the refresh control signal SRFHP having the short logic low pulse ({circle around (7)}).
The refresh signal PREF having the short logic high pulse cannot enable wordlines (not shown) and refresh the memory cells connected to the wordlines. Therefore, a refresh operation is not complete, which causes a failure in the wordlines.